General Videos
| Link | Duration (mm:ss) | Description |
|---|---|---|
| CadEnhance YouTube Channel | - | This is a link to the CadEnhance YouTube Channel |
| CadEnhance ScreenCast Video Channel | - | This is a link to all the public CadEnhance ScreenCast Videos |
| PartBuilder Overview | 08:49 | Video slide show providing overview of PartBuilder features |
| Detailed SDL Slides | 18:02 | Video slide show providing detailed information on SDL |
User Guide Videos
| Link | Duration (mm:ss) | Description |
|---|---|---|
| ScreenCast PartBuilder User Guides | - | This is a link to all the PartBuilder User Guides |
| Symbol Creation Flow | 0:34 | High Level Steps of Symbol Creation |
| Getting Started Building a Part | 5:08 | How to get started with a new part, copying from an existing part or copying an Example Part from CadEnhance |
| The Symbol Creation Pipeline | 5:52 | This video covers the process steps that PartBuilder uses to take the input PinData and create finished Symbols for the selected EDA tools |
| Downloading Sample Parts from CadEnhance | 3:51 | How to download sample parts from the CadEnhance Website |
| Using SIG_RENAME_RULES | 4:25 | How to use SIG_RENAME_RULES to change pinNames without touching vendor data |
| Overriding Pin Types | 8:43 | How to override or define PinTypes when using pinData that does not contain pinTypes or data that contains incorrect pinTypes |
| Intro to the SDL Editor | 14:38 | Introduction to the sdl Editor. This video covers the use of the SDL-EDITOR to edit the SDL for the DDR3 DRAM example part |
| SDL Editor Shortcut Keys | 2:50 | Intro to the SDL Editor ShortCut Keys |
| Working With SDL Include Files | 6:07 | Detailed coverage of creating and using SDL INCLUDE files with the SDL-EDITOR |
| The Power of the ‘Replicate Command in SDL | 6:30 | Shows examples of the use of the `REPLICATE preprocessor command to create multiple symbols in a multi-ported part |
| Create Xilinx Package File with Vivado | 3:51 | How to use Vivado to create a package file for use with the PartBuilder XILINX flows |
| FPGA_LOGICAL vs FPGA_PHYSICAL Flows | 10:50 | Compare and Constrast the FPGA_LOGICAL vs FPGA_PHYSICAL flows from PartBuilder |
| A Look at the ARRIA10_GX160 SDL File | 9:52 | Detailed look at the Symbol Description Language File for an ARRIA10 GX160 device. This SDL was used to create the part in the Build Example in the table below |
| One Step Orcad Symbol Import | 2:22 | How to Import the EDIF symbol file into Orcad/Capture in one simple step |
Build Examples Videos
| Link | Duration (mm:ss) | Description |
|---|---|---|
| Example Builds | - | This is a link to a page containing videos detailing all the required steps to build symbols for certain parts |
| DDR3 DRAM From IBIS Model | 23:49 | All the steps used to build the symbols for the 512Mx16 DDR3 DRAM using the IBIS file to extract pinData. |
| Converting PDF to spreadsheet for TI ADS8294b | 12:09 | This shows the process of converting PDF to spreadsheet using a free online tool and then we use the GENERIC_CSV flow to import the pindata and then go through the rest of the steps requierd to build symbols for the part. |
| Altera MAX10 Part | 11:59 | Create symbols for the Altera MAX10 using the ALTERA MAX10 10M08DC Using the ALTERA_PHYSICAL Flow |
| Broadcom PEX8616 SIMPLE_BGA | 24:30 | Start to finish creation of symbols for a Broacdom PEX8616 device. We convert the pdf pin-table matrix from the Broadcom datasheet and use it as the SIMPLE_BGA input type |
| Building the Altera A10GX160 | 10:10 | Quick video showing the process of building the ALTERA A10GX160 device using ALTERA_PHYSICAL Flow. The ARRIA10_GX160 video in the table above takes an in-depth look at the SDL we used to draw the symbols. |
| Three videos to show power of SDL Replicate and Include files when building different FPGA devices from the same family Building 2 large FPGA devices in <1/2 hour |
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| Xilinx Artix7 484Pin FPGA Start to Finish | 9:41 | All steps required to build Xilinx Artix7 xca75tfgg484 FPGA device starting with using Vivado to create pinData (package) file. |
| Modify Artix7 SDL to use Replicate | 7:43 | Change the SDL for the Artix7 484 pin device to use SDL REPLICATE statements to duplicate the Generic I/O banks and the XCVR I/O banks |
| Build larger Artix7 FPGA from the Existing 484 Pin Project | 8:06 | Quickly build the 1156 Pin Artix7 xc7a200tffg1156 FPGA from the existing xc7a75tffg484 Project by modifying the Bank lists in the REPLICATE Statements |