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Drive Your EDA Tools...

@The Speed Of CadEnhance

You’ve invested big $$$ in your EDA design tools…

CadEnhance Productivity Tools increase their Accuracy and Efficiency

With a price tag  you can afford

Repetitive Tasks Automated...

@ The Speed of CadEnhance

Building high pin count Schematic Symbols?
Connecting large ASICs and Programmable Logic?
Verifying Connectivity?
Creating Hierarchical Designs?
Documenting Design Changes?

Find Out More  

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@The Speed of CadEnhance

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CadEnhance EDA Productivity Tools

 

CadEnhance offers products and services aiding Electrical Engineers and PCB designers in the hardware design process from Schematic Capture through to Manufacturing.

The CadEnhance Tool Set has been instrumental in the design of more than 100 instances of high end, PC Boards for the Telecom, DataCom and Advanced Computing industry over the last 15 years. It has evolved over time to automate the complex, repetitive and error-prone design tasks that face hardware engineers and board designers.

Increase the accuracy and efficiency of your hardware design flows in AllegroHDL, OrCad, Mentor and Altium EDA Tools

Part Builder 

As the Industry migrates to larger parts with increasing pin counts, A tool is needed that can quickly and accurately create symbols to represent those parts in a schematic. 

PartBuilder build symbols for the Allegro-HDL, OrCad,  Mentor dxDesigner/PADs Professional, Eagle and Altium  EDA Tools without consuming a license.

What differentiates PartBuilder from other symbol building tools are the extensive pin-data extraction capabilities, and the Symbol Description Language (SDL).

Quick and accurate pin-data extraction is key to first time success in any board design project.  PartBuilder can extract data from BSDL files, FPGA vendor files, existing symbol files and flexible spreadsheet formats provided by vendors or scraped from pdf datasheets.

The SDL enables the user to describe the layout of pins and symbols at a very high level.  It supports looping constructs and pin-name pattern matching which provide capabilities that designers haven’t seen before. For example using one 45 line SDL file, a user can create the symbol files for any Virtex7 FPGA in the Xilinx part family (some with over 2000 pins), and similar SDL files will provide support for Altera(Intel) and Lattice part families. 

Part Builder with Free Symbol Viewer

SchChk Schematic Checker and Hierarchical Block Builder

Find common errors in Allegro DE-HDL schematics before packaging -Provides succinct error summaries per Hierarchical block -Creates Allegro DeHDL Marker file to allow easy navigation to the errors Build symbols for hierarchical blocks -Replaces Cadence GenView functionality (no Cadence License needed) –reads the layout of I/O Ports  in the schematic page for the block. –move a port in the schematic and the port will move on the block

CadEnhance schChk Schematic Checker with Hierarchical symbol builder/viewer
CadEnhance NetBom Design Revision Comparison Tool with Netlist Conversion Features

NetBom NetList and Bom Diff Tool

Make your Design Reviews more Efficient

Report Differences between 2 Revisions of Allegro De-Hdl Netlists  or BOMS
–distills the differences down to an easy to understand report format  

Convert Allegro DE-HDL Netlists to other Formats

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