Connection Error Checks Across All Blocks and Pages
CadEnhance’s Schematic Checker finds common errors in Cadence® Allegro® Design Entry HDL schematics before packaging. It creates an Allegro marker file that allows the user to easily navigate to all error locations, replaces Allegro Genview function (no license needed), and more.
Schematic Checker reports connection errors using one tab for each block in the design.
The errors are clearly labeled by type and a command is provided to move the user to the coordinate of that error on the selected page.
Schematic Checker also creates an Allegro-HDL marker file for each error that the user can use to directly navigate to find it.
Build Hierarchical Block Symbols
Control pin/port placement by the location of i/o ports within the schematic page.