Schematic SYMBOL Creation Made Easy
Does your team create schematic symbols for Allegro®, Altium®, EAGLE™, Mentor®, OrCAD®, and Zuken® EDA tools?
PartBuilder can help! It provides a much faster, more accurate way to build and maintain high pin count symbol libraries for your current EDA tools.
ACCURATE And Efficient
Scalable performance from 10 to 10,000+ pins.
Smart-FRAC and the Symbol Description Language (SDL) enable the computer to do the majority of the work to build your symbols.
Create symbols for any Altera, MicroSemi, Lattice, and Xilinx FPGA from 100-4000+ pins in under an hour.
Create symbols for processors, switches, ASICs, and other devices in under an hour per thousand pins.
Ultra-fast Pin Data Extraction
PartBuilder extracts pin data from over 20 industry sources, including BSDL, IBIS, and FPGA package files. Flexible spreadsheets can be created by hand or using free online tools to convert PDF data sheets to spreadsheets.
Translate Existing EDA Symbols to Your EDA Tool
Translate existing AllegroHDL, Orcad, or dxDesigner symbols to all supported EDA tools following your library standards.
Use your existing symbols to establish a set of rules to build symbols to your standards. A set of site rules can be maintained to define your company’s symbol standards, ensuring every part is built following your guidelines.
Work Smarter, Not Harder
Symbol Description Language (SDL)
Tell the computer how it should build your symbols. Eliminates interactive dragging and dropping of pins. Place 1000+ power pins across multiple symbols with one statement. Place 32-bit wide bus of diff-pairs with another. Provides unmatched agility defining fractured symbol construction.
PinExplorer views the extracted pin data and interactively creates rules to modify pin attributes without touching the vendors source data.
Smart-FRAC creates the initial SDL template by analyzing the pin data to create groups of busses, diff-pairs and Power pins. It automatically distributes all the device power pins, across the minimum number of symbols needed, while clearly spacing the unique power rails from each other for easy identification and hookup in the schematic.
The SDL-Editor quickly arranges the pin-matches into a user-defined collection of symbols while easily optimizing pin placements with efficient spacing commands.
Create FPGA SYMBOLS 50x Faster
Create flexible collections of symbols for FPGAS ranging from 50-4000+ pins in under an hour.
How is this possible? PartBuilder quickly extracts the pin data including pin-delay from Xilinx, Altera, Lattice, and Microsemi package files, then Smart-FRAC and SDL kick in to finish the job.
simple Part Generation
Select the type of pin data and provide the pin data for extraction
Create rules to rename pins and redefine pin types, if needed
Run Smart-Frac to create initial SDL
Edit SDL to arrange pins around a limitless number of named symbols
Define and edit part property placement and content
Generate the symbols for any enabled EDA tool following your library standards
Release the locally created symbols to your library when the part is ready