Effortlessly connect hundreds of pins with a few mouse clicks
CE-HDL is a suite of tools that plug into Cadence® Allegro® Design Entry HDL to magically add wires, parts and signal names, create and edit Hierarchical Blocks, and tidy up the schematic.
Add Wires, Parts, and Signal Names Like Magic
CE-HDL adds named wires between device pins and hierarchical ports, off-pages or selectable library components. The wire name is created from the symbol pinName and can be altered using powerful rename rules. A prefix or suffix can also be added.
Insert series components into existing wires endpoints.
Copy wire names across the wires using rename rules and a prefix or suffix.
HOw Do you connect your FpGAS?
Open pin report in text editor or Excel
Connect FPGA pin
Find SIG_NAME for pin in pin report
Manually add wire
Manually type then locate SIG_NAME
Add proper off-page/port at end of wire
Repeat previous step for every FPGA pin
Go back and verify the SIG_NAME for every FPGA pin
Assign FPGA pin report file to one of the FPGA symbols
Edit power rail config for part (if you want power connections)
Select wire termination (off-page, IO-port)
Run the “add wires” operation for each group of pins you want to connect
Get some coffee
What about POwer Pins?
CE-HDL lets you define the power connections for a device by editing a simple table that gets created and stored for each part in the design. When you add wires to the power pins, it creates a bussed connection with only one off-page or port per unique net, making it very easy to work with and change the design, if needed.
CONNECT A DDR4 DIMM in five Minutes
Putting it all together, CE-HDL can wire this DDR4 DIMM connector using rename rules to shorten pin names and skip unused pins, and interleave the power and ground connections without the inadvertent shorts which are so easy to create when connecting manually.
And, by the way, PartBuilder easily created this DIMM symbol from the vendor data sheet in <25 minutes.
Bottoms-Up HIERARCHY with CE-HDL and ParTBuilder
CE-HDL integrates with PartBuilder to effortlessly create Allegro-HDL hierarchical designs working from the bottom level, up. Signal names are created from Pin Names and Hierarchical port names are created from Signal names.
Add placeholder hierarchical block (HBLOCK)
Edit HBLOCK schematic
Make connections to hierarchical ports with CE-HDL
Create HBLOCK symbol with PartBuilder
Refresh HBLOCK at top Level
Connect HBLOCK symbols with CE-HDL